1. Field of the Invention
The present invention relates to a printed circuit board (PCB) having a plating pattern buried in a via and a method of manufacturing the same, and, more particularly, to a method of manufacturing a PCB, which includes forming a negative pattern for forming a plating pattern, thus remarkably reducing the generation of plating thickness deviation in a plating process for forming a circuit pattern, and to a PCB having improved electrical signal transmission properties.
2. Description of the Related Art
With the advancement of the electronics industry, the demand for increasing the functionality of electronic components and reducing the size thereof has rapidly increased. In accordance therewith, the density of a circuit pattern of a PCB must increase, and thus various methods of forming a fine circuit pattern have been devised, proposed and applied.
Among the methods of forming a fine circuit pattern, the present invention is intended to provide a PCB having a stabler construction in which a circuit pattern is buried in an insulating layer to thus realize a high density of the circuit pattern, and a manufacturing method thereof.
FIGS. 1A to 1M are cross-sectional views showing the process of manufacturing a PCB according to a conventional technique.
As shown in FIG. 1A, a double-sided copper clad laminate in which a copper foil 3 is formed on both surfaces of an insulating layer 1 is prepared. As shown in FIG. 1B, a via hole 5 is processed using a CNC drill. As shown in FIG. 1C, an electroless plating layer 7 is formed on the inner wall of the via hole 5. As shown in FIG. 1D, the via hole 5 is filled with a paste 9, and, as shown in FIG. 1E, the protruding paste 9 is removed. Thereafter, an etching resist (not shown) is layered and patterned, and then the copper foil 3 and the electroless plating layer 7, which are exposed, are removed, thus manufacturing a double-sided PCB as shown in FIG. 1F.
Next, as shown in FIG. 1G, an additional insulating layer 11 is formed on the upper and lower surfaces of the double-sided PCB, in order to form an additional build-up layer. As shown in FIG. 1H, a blind via hole 13 for exposing the lower circuit layer is processed. Next, as shown in FIG. 1I, an electroless plating layer 15 is formed on the surface of the additional insulating layer 11 and the inner wall of the blind via hole 13, and, as shown in FIG. 1J, a plating resist layer 17 is layered and patterned. Next, as shown in FIG. 1K, electroplating is performed using the electroless plating layer 15 as a lead wire, thus forming a circuit pattern 21 and a via 19 in the openings of the plating resist layer 17. As shown in FIG. 1L, the remaining plating resist layer 17 is removed, and, as shown in FIG. 1M, the exposed electroless plating layer 15 is removed, thereby manufacturing a four-layer PCB.
In the method of manufacturing the four-layer PCB, the circuit pattern of the circuit layer of the double-sided PCB is formed through a subtractive process, and the additional build-up layer is formed through SAP (Semi-Additive Process).
However, as the circuit of a PCB such as a semiconductor substrate becomes finer, the ability to use a subtractive process to form a fine circuit becomes exceeded. Thus, there is an increasing tendency to use SAP or MSAP (Modified Semi-Additive Process) to form the fine circuit.
However, in the case where the circuit layer is formed through SAP or MSAP, the size of the pad of the via 19 is increased, thus making it difficult to realize a fine circuit. To solve this problem, if the size of the via 19 is reduced, another problem of non-plating or delamination of the via 19 may occur.
Also, the case where the circuit pattern 21 is formed through electroplating according to the conventional technique is problematic in that plating deviation, specifically, a thick portion and a thin portion of the plating thickness, may result, and thus the resulting non-uniform resistance may adversely affect the transmission of electrical signals.
Although the plating deviation may result from the distance from the lead wire, etc., the generation thereof is considered to be because an electric field is dispersed on a portion of the PCB having a low wiring density upon electroplating, resulting in a low plating thickness, whereas an electric field is concentrated on the other portion of the PCB having a high wiring density, resulting in a thick signal line thickness.